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Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
DESCRIPTION
Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package.
BUK127-50GT
QUICK REFERENCE DATA
SYMBOL VDS ID PD Tj RDS(ON) PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance MAX. 50 2.1 1.8 150 200 UNIT V A W C m
APPLICATIONS
General purpose switch for driving lamps motors solenoids heaters in automotive systems and other applications.
FEATURES
TrenchMOS output stage Current trip protection Overload protection Overtemperature protection Protection latched reset by input 5 V logic compatible input level Control of output stage and supply of overload protection circuits derived from input Low operating input current permits direct drive by micro-controller ESD protection on all pins Overvoltage clamping for turn off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V CLAMP INPUT
RIG
POWER MOSFET
LOGIC AND PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223
PIN 1 2 3 4 input drain source drain (tab) DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
D TOPFET I
P
1
2
3
S
December 2001
1
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS ID ID II IIRM PD Tstg Tj PARAMETER Continuous drain source voltage Drain current2 Continuous drain current Continuous input current Non-repetitive peak input current Total power dissipation Storage temperature Continuous junction temperature
1
BUK127-50GT
CONDITIONS Ta = 25C clamping tp 1 ms Ta = 25 C normal operation3
MIN. -55 -
MAX. 50 current trip 2.1 3 10 1.8 150 150
UNIT V A A mA mA W C C
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model; C = 250 pF; R = 1.5 k MIN. MAX. 2 UNIT kV
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL EDSM EDRM PARAMETER Non-repetitive clamping energy Repetitive clamping energy CONDITIONS Ta 25 C; IDM ID(TO); inductive load Tsp 125 C; IDM = 1 A; f = 250 Hz MIN. MAX. 100 5 UNIT mJ mJ
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads. Overload protection operates by means of drain current trip or by activating the overtemperature protection. SYMBOL VDDP PARAMETER REQUIRED CONDITION MIN. MAX. 35 UNIT V Protected drain source supply voltage VIS 4 V
THERMAL CHARACTERISTICS
SYMBOL Rth j-sp Rth j-b Rth j-a PARAMETER Thermal resistance Junction to solder point Junction to board4 Junction to ambient CONDITIONS MIN. TYP. 12 40 MAX. 18 70 UNIT K/W K/W K/W
Mounted on any PCB Mounted on PCB of fig. 4
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 Refer to OVERLOAD PROTECTION CHARACTERISTICS. 3 Not in an overload condition with drain current limiting. 4 Temperature measured 1.3 mm from tab.
December 2001
2
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
OUTPUT CHARACTERISTICS
Limits are for -40C Tmb 150C; typicals are for Tmb = 25 C unless otherwise specified SYMBOL PARAMETER Off-state V(CL)DSS IDSS Drain-source clamping voltage CONDITIONS VIS = 0 V ID = 10 mA ID = 200 mA; tp 300 s; 0.01 Drain source leakage current On-state RDS(ON) Drain-source resistance VDS = 40 V Tmb = 25 C VIS 4 V; tp 300 s; 0.01 ID = 100 mA Tmb = 25 C 50 50 MIN.
BUK127-50GT
TYP.
MAX.
UNIT
60 0.1
70 100 10
V V A A m m
150
380 200
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input. Limits are for -40C Tmb 150C; typicals are for Tmb = 25C unless otherwise specified SYMBOL VIS(TO) IIS IISL VISR tlr V(CL)IS RIG PARAMETER Input threshold voltage Input supply current Input supply current Protection reset voltage1 Latch reset time Input clamping voltage Input series resistance2 to gate of power MOSFET CONDITIONS VDS = 5 V; ID = 1 mA Tmb = 25C normal operation; protection latched; reset time tr 100 s VIS1 = 5 V, VIS2 < 1 V II = 1.5 mA Tmb = 25C VIS = 5 V VIS = 4 V VIS = 5 V VIS = 3 V MIN. 0.6 1.1 100 80 1.4 0.7 1.5 10 5.5 TYP. 1.6 220 195 2 1.1 2 40 2.5 MAX. 2.4 2.1 400 330 2.5 1.5 2.5 100 8.5 UNIT V V A A mA mA V s V k
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until reset by the input. SYMBOL ID(TO) PARAMETER Overload protection Drain current trip threshold CONDITIONS VIS = 4 V to 5.5 V Tj = 25C -40C Tj 150C Overtemperature protection Tj(TO) Threshold junction temperature VIS = 4 V to 5.5 V 150 170 C 4 3 8 9 A A MIN. TYP. MAX. UNIT
1 The input voltage below which the overload protection circuits will be reset. 2 Not directly measureable from device terminals.
December 2001
3
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
SWITCHING CHARACTERISTICS
BUK127-50GT
Ta = 25 C; resistive load RL = 50 ; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms SYMBOL td on tr td off tf PARAMETER Turn-on delay time Rise time Turn-off delay time Fall time VIS = 5 V to VIS = 0 V CONDITIONS VIS = 0 V to VIS = 5 V MIN. TYP. 0.5 0.7 3.2 1.6 MAX. 0.9 1.5 6.5 3.5 UNIT s s s s
REVERSE DIODE LIMITING VALUE
SYMBOL IS PARAMETER Continuous forward current CONDITIONS Tmb 25 C; VIS = 0 V MIN. MAX. 2 UNIT A
REVERSE DIODE CHARACTERISTICS
Limits are for -40C Tmb 150C; typicals are for Tmb = 25C unless otherwise specified SYMBOL VSDO trr PARAMETER Forward voltage Reverse recovery time CONDITIONS IS = 2 A; VIS = 0 V; tp = 300 s not applicable1 MIN. TYP. 0.83 MAX. 1.1 UNIT V -
1 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
December 2001
4
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
MECHANICAL DATA
Plastic surface mounted package; collector pad for good heat transfer; 4 leads
BUK127-50GT
SOT223
D
B
E
A
X
c y HE b1 vMA
4
Q A A1
1
e1 e
2
bp
3
wM B detail X
Lp
0
2 scale
4 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.8 1.5 A1 0.10 0.01 bp 0.80 0.60 b1 3.1 2.9 c 0.32 0.22 D 6.7 6.3 E 3.7 3.3 e 4.6 e1 2.3 HE 7.3 6.7 Lp 1.1 0.7 Q 0.95 0.85 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT223
REFERENCES IEC JEDEC EIAJ SC-73
EUROPEAN PROJECTION
ISSUE DATE 97-02-28 99-09-13
Fig.2. SOT223 surface mounting package1.
1 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8". Net Mass: 0.11 g
December 2001
5
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
MOUNTING INSTRUCTIONS
Dimensions in mm.
3.8 min
BUK127-50GT
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
1.5 min
18
60 9
2.3 1.5 min (3x) 6.3
4.6
4.5
10
1.5 min
4.6
7 15 50
Fig.3. Soldering pattern for surface mounting.
Fig.4. PCB for thermal resistance and power rating. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick).
December 2001
6
Rev 2.000
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK127-50GT
DEFINITIONS
DATA SHEET STATUS DATA SHEET STATUS1 Objective data PRODUCT STATUS2 Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A
Preliminary data
Qualification
Product data
Production
Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design. 2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
December 2001
7
Rev 2.000

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